The invention relates to data processing hardware that is reconfigurable to perform different operations.
FIG. 1 illustrates a half of a digital signal processing (DSP) block in a Stratix® II field programmable gate array (FPGA) device from Altera Corporation of San Jose, Calif. The part-block 10 shown in FIG. 1 has four input paths 12 to 18 and three output paths 20 to 24. The part-block 10 also comprises two multipliers 26 and 28 and an adder 30. Optional input registers 12a to 18a are shown in the diagram, but optional pipelining and output registers have not been shown. Multiplier 26 multiplies together the values received on input paths 12 and 14 and provides the result on output path 20. Likewise, multiplier 28 multiplies together the values received on input paths 16 and 18 and provides the result on output path 24. The values conveyed on the output paths 20 and 24 are also provided as inputs to the adder 30 by paths 32 and 34, respectively. The adder 30 can be configured in known fashion to either add its inputs together or to subtract the value received on path 34 from the value received on path 32. The adder 30 also includes functionality to enable it to perform summation or accumulation of additions/subtractions performed over successive clock cycles. The output of the adder 30 is provided on output path 22.
It is commonly desired in DSP routines to perform an addition prior to multiplication. That is to say, to perform a calculation of the type (A+B)×C. One option for catering for that kind of operation is to adapt the structure shown in FIG. 1 to include one or more additional adders in front of the multipliers 26 and 28 but this has the consequence of requiring additional input paths to the part-block 10 which would undesirably increase the amount of silicon area taken up by the part-block.